1. Field of the Invention
The present invention relates to a method for forming different area vias of dynamic random access memory and more particularly to a method that vias in a cell region and in a periphery circuit region are patterned and formed in a mask and in same etching process.
2. Description of the Prior Art
In contemporary semiconductor industry, semiconductor memory is a popular and important product for widely and effective application. In particular, dynamic random access memory (DRAM) is more broadly used in microelectronic product for high-integration of DRAM than other semiconductor memory.
There are both cell region and periphery circuit region in the DRAM, the cell region comprises metal oxide semiconductors (MOS) and capacitors, and is used to storage messages. In comparison, the periphery circuit region comprises gates and conductive lines, and is used to connect the cell region and related elements. Moreover, though both gates of the cell region and gates of the periphery circuit region can be formed simultaneously and only a mask is required to define locations of these gates. Nevertheless, many semiconductor structures are formed separated in these two regions and then required mask, photolithography and related fabrication are prepared and preformed in each individual region. Thus, the throughput of DRAM fabrication is restricted by duplicate process in two regions. Then an incidental disadvantageous is that consumed material also is increased by duplicate process in these two regions.
An obvious example is that vias in different regions can not be opened at the same time and two masks are necessary to pattern locations of vias. Conventional fabrication of vias comprises following steps: First, as shown in FIG. 1A, a plurality of cell gates are formed in the cell region and a plurality of periphery circuit gates are formed in the periphery circuit region, where these gates are formed on a substrate 10. Moreover, each gate of cell region comprises a conductive layer 12, a polycide layer 13 and a passivation layer 14. In comparison, each gate of periphery circuit region comprises a conductive layer 15, a polycide layer 16 and a passivation layer 17. Therewith a first dielectric layer 11 is formed over substrate 10 and covers all gates, and then a second dielectric layer 18 is formed over first dielectric layer 11. Subsequently, a plurality of spacers are formed in sidewalls of all gates.
Afterwards, a third dielectric layer 19 is formed over substrate 10 and covers gates of cell region and gates of periphery circuit region. Subsequently, vias in cell region are formed by photolithography method and etching process as FIG. 1B shows.
Afterwards, as shown in FIG. 1C, another dielectric layer 195 is formed over third dielectric layer 19 and fills vias in cell region. Then vias in periphery circuit region are formed by photolithography method and etching process.
Obviously, there are two mask are necessary in conventional fabrication of vias, and required photolithography and etching process also are double for duplicate fabrication in cell region and periphery circuit region.
For these foregoing reasons, it is obvious that throughput of DRAM fabrication is degraded by duplicate process, and then it is profitable and necessary to develop new fabrication that forming DRAM without duplicate process. In addition, it is more beneficial to form vias of cell region and vias of periphery circuit region at the same time, where an incidental advantageous that only a mask and a photolithography are necessary.